1. Field of the Invention
The present invention relates to high speed sensing for integrated circuit memory devices; and particularly circuits and methods for limiting the effects of device mismatch in sense amplifiers.
2. Description of Related Art
Sense amplifiers in integrated circuits are often designed to detect a difference in voltage across first and second inputs. The first input is connected to a memory cell via decoding circuits that select a memory cell. If the memory cell provides a differential output, such as provided by typical SRAM memory, then the second input is coupled to the complementary output of the memory cell. If the memory cell is single ended, then the second input is coupled to a reference voltage.
Circuits that detect a difference between two inputs include latch circuits that comprise a pair of cross-coupled inverters. The inverters are designed so that the switching points are balanced to switch according to desired levels of the first and second inputs of the latch circuit. However, in the manufacturing of integrated circuits, the inverters do not match perfectly. So, the sense amplifier must be designed to account for potential mismatch. Also, the latches have relatively high switching points, so low level signals, such as signals encountered in source side sensing in memory devices, must be amplified before latching.
One way to account for potential mismatch is to provide a high gain input stage for the sense amplifier. This increases the speed of changes in voltage on the inputs to the latch circuit, so that the time required to develop the margin is short. Another way to account for mismatch is to control the timing of the latch, so that it operates to capture the state of the first and second inputs after the voltage levels on the first and second inputs have reached a stable latch point above the margin required to account for potential mismatches. See, for example, U.S. patent application Publication No. U.S. 2003/0198112 A1, entitled VARIABLE DELAY COMPENSATION FOR DATA-DEPENDENT MISMATCH IN CHARACTERISTIC OF OPPOSING DEVICES OF A SENSE AMPLIFIER, filed Apr. 16, 2002, by Eleyan et al.
The problem presented by mismatch is aggravated by the advances in clock speeds, and reductions in supply voltages in modern integrated circuits. In order for sense amplifiers to work reliably, the timing of the latch circuit must be set to allow for the mismatch margins. Because the mismatch is difficult to predict, and can vary over time, the timing must account for worst-case conditions. The timing margin to account for mismatch becomes a significant limit on increasing clock speeds for the latch circuits. Likewise, mismatch in the switching levels of latch circuits requires that they be designed with voltage headroom to account for worst-case mismatch. Thus, the voltage headroom required to account for mismatch becomes a significant limit on low voltage operation of the devices.
Also, the addition of high gain stages can aggravate the mismatch problem, because the gain stages may also suffer from mismatch. The mismatch in the high gain stage can affect the accuracy and timing of the latch stage of the sense amplifier.
Thus, it is desirable to provide a sense amplifier design that reduces the problems associated with mismatch, allowing low voltage and high-speed operation.